Use and Manage Microcode Updates
MCUP lets you use and manage microcode updates for Intel P6 and NetBurst micro-architecture processors.
a) It displays information about the CPU and the currently loaded microcode update.
b) It determines if your system has the capability to dynamically integrate processor-specific microcode updates into the BIOS. If so, your system has memory locations in NVRAM reserved for microcode updates. MCUP will display the microcode updates currently stored there, and lets you flash new microcode updates to these locations.
c) It lets you load a microcode update directly to the CPU. This is temporary; it will be gone after the next reset. After loading the microcode update MCUP lets you launch (boot) an operating system from floppy or hard disk without causing a reset.
d) It lets you organize microcode updates in database files. Microcode updates can be copied, deleted and sorted (doubles are thereby removed automatically). Supported file formats are the frequent plain type (only microcode updates) and a type with a header preceding the microcode updates.
e) It can extract microcode update databases from most Award BIOS binaries and save them to a file.
Intel P6 and NetBurst micro-architecture processors have a feature called reprogrammable microcode, which allows changing the behavior of the CPU by loading a microcode update into a CPU internal volatile memory. By supplying microcode updates to its partners (i.e. main board and system manufacturers), Intel can correct processor bugs in a very efficient way.
The reprogrammable microcode feature seems to be Intel's reaction to the FDIV bug that occurred in it's 60 to 100 MHz Pentium CPUs and has been included in all of the company's succeeding 32-Bit desktop processors, starting with the Pentium Pro.
The FDIV bug was publicized by a user in Oct 1994. Intel first denied its existence, later acknowledged it as "P54C Erratum 23" and agreed to replace faulty processors. While many argue that the bug wasn't such a big thing, most agree that Intel's handling of it caused a PR disaster.
P6 architecture processors include the Pentium Pro, Pentium II, Pentium II Xeon, Celeron, Pentium III and the Pentium III Xeon. NetBurst architecture processors include the Celeron (478-pin), the Pentium 4, Xeon and Xeon MP.
Since the CPU loads a microcode update into an internal volatile memory, the update is lost after every reset and must be reloaded. Ideally this is done early in the boot process, which is why normally the BIOS takes care of this as one of it's POST (Power On Self Test) tasks while it initializes the system. If possible, the BIOS retrieves the required microcode update from a database that's stored in the NVRAM together with the BIOS code. If it can't find a microcode update suited for the CPU, no update is loaded.
Flashing a Microcode Update
One way to incorporate additional and newer microcode updates into the database is by performing a BIOS update. For that, you generally need a suitable BIOS update from the motherboard manufacturer. It is possible to build your own BIOS update, for example with a tool like CBROM if you have an Award BIOS. But this can by tricky, so this solution is not for everybody. Also, there is always a certain risk involved with BIOS updates.
As an alternative, many BIOS versions support an interface for the dynamic integration of microcode updates. If a BIOS has this interface, the BIOS manufacturer has reserved one or more memory locations for microcode updates in NVRAM that can be flashed independently of the BIOS. This method requires a software that accesses the interface (i.e. MCUP) and a database containing the desired microcode update(s). Intel restricts access to microcode updates, but there are several archives on the internet, like MCU.DAT, PEP.DAT, PER*.PDB or REALL.COD.
What do they do?
The details, of which bugs Intel fixes with microcode updates are a secret, shared only with Intel's partners and kept under NDA. The logical place to look for this information would be the Intel processor specification updates (http://developer.intel.com), but the sections on microcode updates have been omitted from the publicly available data. However, what the specification updates do list are bugs (called errata) and the processor core steppings in which they occur or have been fixed. Assuming that there generally are no secret bugs, the microcode updates should tend to the problems that are listed as not fixed in hardware. Although Intel denies this, some speculate that microcode updates also play a role in determining processor capabilities, for example if a feature like Hyper-Threading is enabled or not.